BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121115T003000Z
DTEND:20121115T020000Z
LOCATION:255-A
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: The Intel Xeon Phi will offer tremendous performance and efficiency for highly data-parallel applications when it becomes available in late 2012. The Xeon Phi will debut for HPC in the NSF-funded Stampede system, which will offer ~10PF peak performance in January 2013. Programming and porting for Xeon Phi coprocessors is accomplished with standard, widely used programing toolsFortran, C/C++, OpenMP, and MPI. In addition, a variety of usage modes are available which offer tradeoffs between code porting speed and raw application performance. This session will introduce attendees to the Phi processor, various programming models, and the Stampede system at TACC.
SUMMARY:Intel MIC Processors and the Stampede Petascale Computing System
PRIORITY:3
END:VEVENT
END:VCALENDAR
BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121115T003000Z
DTEND:20121115T020000Z
LOCATION:255-A
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: The Intel Xeon Phi will offer tremendous performance and efficiency for highly data-parallel applications when it becomes available in late 2012. The Xeon Phi will debut for HPC in the NSF-funded Stampede system, which will offer ~10PF peak performance in January 2013. Programming and porting for Xeon Phi coprocessors is accomplished with standard, widely used programing toolsFortran, C/C++, OpenMP, and MPI. In addition, a variety of usage modes are available which offer tradeoffs between code porting speed and raw application performance. This session will introduce attendees to the Phi processor, various programming models, and the Stampede system at TACC.
SUMMARY:Intel MIC Processors and the Stampede Petascale Computing System
PRIORITY:3
END:VEVENT
END:VCALENDAR