BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121113T233000Z
DTEND:20121114T000000Z
LOCATION:155-C
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: DRAM technology has been utilized as main memory in microprocessor-based systems for decades. From the early days of frequency scaling, the gap has been growing between the DRAM performance improvement rate versus the processor data consumption rate. This presentation will show several advantages of using Microns Hybrid Memory Cube (HMC) technology. HMC is a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections. The HMC concept is completely re-architected, redistributing the normal DRAM functions while delivering: =0A=0AScalable System Architectures:  =0AFlexible topologies (expandability)  =0AAbstraction - Future memory process scaling and challenges=0A=0APerformance: =0AHigher effective DRAM bandwidth  =0ALower DRAM system latency =0AIncreased DRAM random request rate=0A=0AEnergy (Power-Efficient Architectures): =0ALower DRAM energy per useful unit of work done  =0AReduced data movement=0A=0ADependability (RAS): =0AIn-field repair capability =0AInternal DRAM ECC
SUMMARY:Hybrid Memory Cube (HMC):  A New Paradigm for System Architecture Design
PRIORITY:3
END:VEVENT
END:VCALENDAR
BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121113T233000Z
DTEND:20121114T000000Z
LOCATION:155-C
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: DRAM technology has been utilized as main memory in microprocessor-based systems for decades. From the early days of frequency scaling, the gap has been growing between the DRAM performance improvement rate versus the processor data consumption rate. This presentation will show several advantages of using Microns Hybrid Memory Cube (HMC) technology. HMC is a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections. The HMC concept is completely re-architected, redistributing the normal DRAM functions while delivering: =0A=0AScalable System Architectures:  =0AFlexible topologies (expandability)  =0AAbstraction - Future memory process scaling and challenges=0A=0APerformance: =0AHigher effective DRAM bandwidth  =0ALower DRAM system latency =0AIncreased DRAM random request rate=0A=0AEnergy (Power-Efficient Architectures): =0ALower DRAM energy per useful unit of work done  =0AReduced data movement=0A=0ADependability (RAS): =0AIn-field repair capability =0AInternal DRAM ECC
SUMMARY:Hybrid Memory Cube (HMC):  A New Paradigm for System Architecture Design
PRIORITY:3
END:VEVENT
END:VCALENDAR