BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121115T203000Z
DTEND:20121115T210000Z
LOCATION:355-D
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: Memory access latency is often a crucial performance limitation for high performance computing. Prefetching is one of the strategies used by system designers to bridge the processor-memory gap. This paper describes a new innovative list prefetching feature introduced in the IBM Blue Gene/Q supercomputer. The list prefetcher records the L1 cache miss addresses and prefetches them in the next iteration. The evaluation shows this list prefetching mechanism reduces L1 cache misses and improves the performance for high performance computing applications with repeating non-uniform memory access patterns. Its performance is compatible with classic stream prefetcher when properly configured.
SUMMARY:Application Data Prefetching on the IBM Blue Gene/Q Supercomputer
PRIORITY:3
END:VEVENT
END:VCALENDAR
BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121115T203000Z
DTEND:20121115T210000Z
LOCATION:355-D
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: Memory access latency is often a crucial performance limitation for high performance computing. Prefetching is one of the strategies used by system designers to bridge the processor-memory gap. This paper describes a new innovative list prefetching feature introduced in the IBM Blue Gene/Q supercomputer. The list prefetcher records the L1 cache miss addresses and prefetches them in the next iteration. The evaluation shows this list prefetching mechanism reduces L1 cache misses and improves the performance for high performance computing applications with repeating non-uniform memory access patterns. Its performance is compatible with classic stream prefetcher when properly configured.
SUMMARY:Application Data Prefetching on the IBM Blue Gene/Q Supercomputer
PRIORITY:3
END:VEVENT
END:VCALENDAR