BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121114T001500Z
DTEND:20121114T020000Z
LOCATION:East Entrance
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: Heterogenous architectures are becoming an increasingly relevant component for High Performance Computing: they combine the computational power of multi-core processors with the flexibility of reconfigurable co-processor boards. Such boards are often composed of a set of standard Field Programmable Gate Arrays (FPGAs), coupled with a distributed memory architecture. This allows the concurrent execution of memory accesses. Nevertheless, since the execution latency of these operations may be unknown at compile-time, the synthesis of such parallelizing accelerators becomes a complex task. In fact, standard approaches require the construction of Finite State Machines whose complexity, in terms of number of states and transitions, increases exponentially with respect to the number of unbounded operations that may execute concurrently. We propose an adaptive architecture for such accelerators which overcome this limitation, while exploiting the available parallelism. The proposed design methodology is compared with FSM-based approaches by means of a motivational example.
SUMMARY:Speeding-Up Memory Intensive Applications Through Adaptive Hardware Accelerators
PRIORITY:3
END:VEVENT
END:VCALENDAR
BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20121114T001500Z
DTEND:20121114T020000Z
LOCATION:East Entrance
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: Heterogenous architectures are becoming an increasingly relevant component for High Performance Computing: they combine the computational power of multi-core processors with the flexibility of reconfigurable co-processor boards. Such boards are often composed of a set of standard Field Programmable Gate Arrays (FPGAs), coupled with a distributed memory architecture. This allows the concurrent execution of memory accesses. Nevertheless, since the execution latency of these operations may be unknown at compile-time, the synthesis of such parallelizing accelerators becomes a complex task. In fact, standard approaches require the construction of Finite State Machines whose complexity, in terms of number of states and transitions, increases exponentially with respect to the number of unbounded operations that may execute concurrently. We propose an adaptive architecture for such accelerators which overcome this limitation, while exploiting the available parallelism. The proposed design methodology is compared with FSM-based approaches by means of a motivational example.
SUMMARY:Speeding-Up Memory Intensive Applications Through Adaptive Hardware Accelerators
PRIORITY:3
END:VEVENT
END:VCALENDAR