SCHEDULE: NOV 10-16, 2012
When viewing the Technical Program schedule, on the far righthand side is a column labeled "PLANNER." Use this planner to build your own schedule. Once you select an event and want to add it to your personal schedule, just click on the calendar icon of your choice (outlook calendar, ical calendar or google calendar) and that event will be stored there. As you select events in this manner, you will have your own schedule to guide you through the week.
Intel MIC Processors and the Stampede Petascale Computing System
SESSION: Intel MIC Processors and the Stampede Petascale Computing System
EVENT TYPE: Birds of a Feather
TIME: 5:30PM - 7:00PM
SESSION LEADER(S):John (Jay) R. Boisseau, Dan C. Stanzione, Karl W. Schulz
ROOM:255-A
ABSTRACT:
The Intel Xeon Phi will offer tremendous performance and efficiency for highly data-parallel applications when it becomes available in late 2012. The Xeon Phi will debut for HPC in the NSF-funded Stampede system, which will offer ~10PF peak performance in January 2013. Programming and porting for Xeon Phi coprocessors is accomplished with standard, widely used programing toolsFortran, C/C++, OpenMP, and MPI. In addition, a variety of usage modes are available which offer tradeoffs between code porting speed and raw application performance. This session will introduce attendees to the Phi processor, various programming models, and the Stampede system at TACC.
Session Leader Details:
John (Jay) R. Boisseau (Primary Session Leader) - Texas Advanced Computing Center
Dan C. Stanzione (Secondary Session Leader) - Texas Advanced Computing Center
Karl W. Schulz (Secondary Session Leader) - Texas Advanced Computing Center
Click here to download .ics calendar file
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Intel MIC Processors and the Stampede Petascale Computing System
SESSION: Intel MIC Processors and the Stampede Petascale Computing System
EVENT TYPE:
TIME: 5:30PM - 7:00PM
SESSION LEADER(S):John (Jay) R. Boisseau, Dan C. Stanzione, Karl W. Schulz
ROOM:255-A
ABSTRACT:
The Intel Xeon Phi will offer tremendous performance and efficiency for highly data-parallel applications when it becomes available in late 2012. The Xeon Phi will debut for HPC in the NSF-funded Stampede system, which will offer ~10PF peak performance in January 2013. Programming and porting for Xeon Phi coprocessors is accomplished with standard, widely used programing toolsFortran, C/C++, OpenMP, and MPI. In addition, a variety of usage modes are available which offer tradeoffs between code porting speed and raw application performance. This session will introduce attendees to the Phi processor, various programming models, and the Stampede system at TACC.
Session Leader Details:
John (Jay) R. Boisseau (Primary Session Leader) - Texas Advanced Computing Center
Dan C. Stanzione (Secondary Session Leader) - Texas Advanced Computing Center
Karl W. Schulz (Secondary Session Leader) - Texas Advanced Computing Center
Click here to download .ics calendar file