SC12 Home > SC12 Schedule > SC12 Presentation - Co-design Architecture and Co-design Efforts for Exascale: Status and Next Steps

SCHEDULE: NOV 10-16, 2012

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ENTIRE WEEK SATURDAY SUNDAY MONDAY TUESDAY WEDNESDAY THURSDAY FRIDAY

Co-design Architecture and Co-design Efforts for Exascale: Status and Next Steps

SESSION: Co-design Architecture and Co-design Efforts for Exascale: Status and Next Steps

EVENT TYPE: Birds of a Feather

TIME: 5:30PM - 7:00PM

SESSION LEADER(S):Sudip Dosanjh, Marie-Christine Sawley, Gilad Shainer

ROOM:355-A

ABSTRACT:
Pathfinding for Exascale recently started in many nations: a DOE program in U.S.A., Exascale projects funded by FP7 in Europe, partnering initiatives between Intel and European government research institutions, national efforts in Japan/China are good examples. The co-design concept developed by the embedded community is a key HPC strategy for reaching Exascale. The BOF will focus on the most relevant experiences and commonalities in applying co-design to HPC, and identify gaps in open research that fuel further developments. A particular example of co-design discussed is the co-development of application communication libraries and the underlying hardware interconnect to overcome scalability issues.

Session Leader Details:

Sudip Dosanjh (Primary Session Leader) - Lawrence Berkeley National Laboratory

Marie-Christine Sawley (Secondary Session Leader) - Intel Corporation

Gilad Shainer (Secondary Session Leader) - HPC Advisory Council

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