SC12 Home > SC12 Schedule > SC12 Presentation - Application Data Prefetching on the IBM Blue Gene/Q Supercomputer

SCHEDULE: NOV 10-16, 2012

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Application Data Prefetching on the IBM Blue Gene/Q Supercomputer

SESSION: Memory Systems

EVENT TYPE: Papers

TIME: 1:30PM - 2:00PM

SESSION CHAIR: Jaejin Lee

AUTHOR(S):IHsin Chung, Changhoan Kim, Hui-Fang Wen, Guojing Cong

ROOM:355-D

ABSTRACT:
Memory access latency is often a crucial performance limitation for high performance computing. Prefetching is one of the strategies used by system designers to bridge the processor-memory gap. This paper describes a new innovative list prefetching feature introduced in the IBM Blue Gene/Q supercomputer. The list prefetcher records the L1 cache miss addresses and prefetches them in the next iteration. The evaluation shows this list prefetching mechanism reduces L1 cache misses and improves the performance for high performance computing applications with repeating non-uniform memory access patterns. Its performance is compatible with classic stream prefetcher when properly configured.

Chair/Author Details:

Jaejin Lee (Chair) - Seoul National University

IHsin Chung - IBM T.J. Watson Research Center

Changhoan Kim - IBM T.J. Watson Research Center

Hui-Fang Wen - IBM T.J. Watson Research Center

Guojing Cong - IBM T.J. Watson Research Center

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Application Data Prefetching on the IBM Blue Gene/Q Supercomputer

SESSION: Memory Systems

EVENT TYPE:

TIME: 1:30PM - 2:00PM

SESSION CHAIR: Jaejin Lee

AUTHOR(S):IHsin Chung, Changhoan Kim, Hui-Fang Wen, Guojing Cong

ROOM:355-D

ABSTRACT:
Memory access latency is often a crucial performance limitation for high performance computing. Prefetching is one of the strategies used by system designers to bridge the processor-memory gap. This paper describes a new innovative list prefetching feature introduced in the IBM Blue Gene/Q supercomputer. The list prefetcher records the L1 cache miss addresses and prefetches them in the next iteration. The evaluation shows this list prefetching mechanism reduces L1 cache misses and improves the performance for high performance computing applications with repeating non-uniform memory access patterns. Its performance is compatible with classic stream prefetcher when properly configured.

Chair/Author Details:

Jaejin Lee (Chair) - Seoul National University

IHsin Chung - IBM T.J. Watson Research Center

Changhoan Kim - IBM T.J. Watson Research Center

Hui-Fang Wen - IBM T.J. Watson Research Center

Guojing Cong - IBM T.J. Watson Research Center

Add to iCal  Click here to download .ics calendar file

Add to Outlook  Click here to download .vcs calendar file

Add to Google Calendarss  Click here to add event to your Google Calendar