SCHEDULE: NOV 10-16, 2012
When viewing the Technical Program schedule, on the far righthand side is a column labeled "PLANNER." Use this planner to build your own schedule. Once you select an event and want to add it to your personal schedule, just click on the calendar icon of your choice (outlook calendar, ical calendar or google calendar) and that event will be stored there. As you select events in this manner, you will have your own schedule to guide you through the week.
Unleashing the High Performance and Low Power of Multi-Core DSPs for General-Purpose HPC
SESSION: Maximizing Performance on Multi-Core and Many-Core Architectures
EVENT TYPE: Papers
TIME: 1:30PM - 2:00PM
SESSION CHAIR: Atsushi Hori
AUTHOR(S):Francisco D. Igual, Murtaza Ali, Arnon Friedmann, Eric Stotzer, Timothy Wentz, Robert A. van de Geijn
ROOM:255-BC
ABSTRACT:
Take a multicore Digital Signal Processor (DSP) chip
designed for cellular base stations and radio network controllers,
add floating-point capabilities to support 4G networks, and out
of thin air a HPC engine is born. The potential for HPC is clear:
It promises 128 GFLOPS (single precision) for 10 Watts; It is
used in millions of network related devices and hence benefits
from economies of scale; It should be simpler to program than
a GPU. Simply put, it is fast, green, and cheap. But is it easy to
use? In this paper, we show how this potential can be applied to
general-purpose high performance computing, more specifically
to dense matrix computations, without major changes in existing
codes and methodologies, and with excellent performance and
power consumption numbers.
Chair/Author Details:
Atsushi Hori (Chair) - RIKEN
Francisco D. Igual - Texas Advanced Computing Center
Murtaza Ali - Texas Instruments
Arnon Friedmann - Texas Instruments
Eric Stotzer - Texas Instruments
Timothy Wentz - University of Illinois at Urbana-Champaign
Robert A. van de Geijn - University of Texas at Austin
Click here to download .ics calendar file
Click here to download .vcs calendar file
Click here to add event to your Google Calendar
Unleashing the High Performance and Low Power of Multi-Core DSPs for General-Purpose HPC
SESSION: Maximizing Performance on Multi-Core and Many-Core Architectures
EVENT TYPE:
TIME: 1:30PM - 2:00PM
SESSION CHAIR: Atsushi Hori
AUTHOR(S):Francisco D. Igual, Murtaza Ali, Arnon Friedmann, Eric Stotzer, Timothy Wentz, Robert A. van de Geijn
ROOM:255-BC
ABSTRACT:
Take a multicore Digital Signal Processor (DSP) chip
designed for cellular base stations and radio network controllers,
add floating-point capabilities to support 4G networks, and out
of thin air a HPC engine is born. The potential for HPC is clear:
It promises 128 GFLOPS (single precision) for 10 Watts; It is
used in millions of network related devices and hence benefits
from economies of scale; It should be simpler to program than
a GPU. Simply put, it is fast, green, and cheap. But is it easy to
use? In this paper, we show how this potential can be applied to
general-purpose high performance computing, more specifically
to dense matrix computations, without major changes in existing
codes and methodologies, and with excellent performance and
power consumption numbers.
Chair/Author Details:
Atsushi Hori (Chair) - RIKEN
Francisco D. Igual - Texas Advanced Computing Center
Murtaza Ali - Texas Instruments
Arnon Friedmann - Texas Instruments
Eric Stotzer - Texas Instruments
Timothy Wentz - University of Illinois at Urbana-Champaign
Robert A. van de Geijn - University of Texas at Austin
Click here to download .ics calendar file