SCHEDULE: NOV 10-16, 2012
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Automatic Generation of Software Pipelines for Heterogeneous Parallel Systems
SESSION: GPU Programming Models and Patterns
EVENT TYPE: Papers
TIME: 2:00PM - 2:30PM
SESSION CHAIR: Michael A. Heroux
AUTHOR(S):Jacques A. Pienaar, Anand Raghunathan, Srimat Chakradhar
ROOM:355-EF
ABSTRACT:
Pipelining is a well-known approach to increasing parallelism and performance. We address the problem of software pipelining for heterogeneous parallel platforms that consist of different multi-core and many-core processing units. In this context, pipelining involves two key steps---partitioning an application into stages and mapping and scheduling the stages onto the processing units of the heterogeneous platform. We show that the inter-dependency between these steps is a critical challenge that must be addressed in order to achieve high performance. We propose an Automatic Heterogeneous Pipelining framework (AHP) that automatically generates an optimized pipelined implementation of a program from an annotated unpipelined specification. Across three complex applications (image classification, object detection, and document retrieval) and two heterogeneous platforms (Intel Xeon multi-core CPUs with Intel MIC and NVIDIA GPGPU accelerators), AHP achieves a throughput improvement of up to 1.53x (1.37x on average) over a heterogeneous baseline that exploits data and task parallelism.
Chair/Author Details:
Michael A. Heroux (Chair) - Sandia National Laboratories
Jacques A. Pienaar - Purdue University
Anand Raghunathan - Purdue University
Srimat Chakradhar - NEC Laboratories America
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Automatic Generation of Software Pipelines for Heterogeneous Parallel Systems
SESSION: GPU Programming Models and Patterns
EVENT TYPE:
TIME: 2:00PM - 2:30PM
SESSION CHAIR: Michael A. Heroux
AUTHOR(S):Jacques A. Pienaar, Anand Raghunathan, Srimat Chakradhar
ROOM:355-EF
ABSTRACT:
Pipelining is a well-known approach to increasing parallelism and performance. We address the problem of software pipelining for heterogeneous parallel platforms that consist of different multi-core and many-core processing units. In this context, pipelining involves two key steps---partitioning an application into stages and mapping and scheduling the stages onto the processing units of the heterogeneous platform. We show that the inter-dependency between these steps is a critical challenge that must be addressed in order to achieve high performance. We propose an Automatic Heterogeneous Pipelining framework (AHP) that automatically generates an optimized pipelined implementation of a program from an annotated unpipelined specification. Across three complex applications (image classification, object detection, and document retrieval) and two heterogeneous platforms (Intel Xeon multi-core CPUs with Intel MIC and NVIDIA GPGPU accelerators), AHP achieves a throughput improvement of up to 1.53x (1.37x on average) over a heterogeneous baseline that exploits data and task parallelism.
Chair/Author Details:
Michael A. Heroux (Chair) - Sandia National Laboratories
Jacques A. Pienaar - Purdue University
Anand Raghunathan - Purdue University
Srimat Chakradhar - NEC Laboratories America
Click here to download .ics calendar file