SCHEDULE: NOV 10-16, 2012
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Impact of Integer Instructions in Floating Point Applications
SESSION: Research Poster Reception
EVENT TYPE: Posters and Electronic Posters
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Torsten Hoefler
AUTHOR(S):Hisanobu Tomari, Kei Hiraki
ROOM:East Entrance
ABSTRACT:
The performance of floating-point oriented applications are determined not only by the performance of floating-point instructions, but also by the speed of integer instruction execution. Dynamic instruction trace of NAS Parallel Benchmarks (NPB) workloads show that integer instructions are often executed more than floating-point instructions in the floating-point application benchmark.
Some vendors are taking the SIMD-only strategy where integer performance stays the same as generations-old ones, while floating-point application performance is increased using SIMD instructions. We show that there is a limit for this approach and that the slow integer execution has a huge impact on the per-socket NPB scores. When these performance is compared to other historic processors, we found that some of the latest processors can be improved by using the known techniques to accelerate the integer performance.
Chair/Author Details:
Torsten Hoefler (Chair) - ETH Zurich
Hisanobu Tomari - University of Tokyo
Kei Hiraki - University of Tokyo
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Impact of Integer Instructions in Floating Point Applications
SESSION: Research Poster Reception
EVENT TYPE:
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Torsten Hoefler
AUTHOR(S):Hisanobu Tomari, Kei Hiraki
ROOM:East Entrance
ABSTRACT:
The performance of floating-point oriented applications are determined not only by the performance of floating-point instructions, but also by the speed of integer instruction execution. Dynamic instruction trace of NAS Parallel Benchmarks (NPB) workloads show that integer instructions are often executed more than floating-point instructions in the floating-point application benchmark.
Some vendors are taking the SIMD-only strategy where integer performance stays the same as generations-old ones, while floating-point application performance is increased using SIMD instructions. We show that there is a limit for this approach and that the slow integer execution has a huge impact on the per-socket NPB scores. When these performance is compared to other historic processors, we found that some of the latest processors can be improved by using the known techniques to accelerate the integer performance.
Chair/Author Details:
Torsten Hoefler (Chair) - ETH Zurich
Hisanobu Tomari - University of Tokyo
Kei Hiraki - University of Tokyo
Click here to download .ics calendar file