SCHEDULE: NOV 10-16, 2012
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Speeding-Up Memory Intensive Applications Through Adaptive Hardware Accelerators
SESSION: Research Poster Reception
EVENT TYPE: Posters and Electronic Posters
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Torsten Hoefler
AUTHOR(S):Vito Giovanni Castellana, Fabrizio Ferrandi
ROOM:East Entrance
ABSTRACT:
Heterogenous architectures are becoming an increasingly relevant component for High Performance Computing: they combine the computational power of multi-core processors with the flexibility of reconfigurable co-processor boards. Such boards are often composed of a set of standard Field Programmable Gate Arrays (FPGAs), coupled with a distributed memory architecture. This allows the concurrent execution of memory accesses. Nevertheless, since the execution latency of these operations may be unknown at compile-time, the synthesis of such parallelizing accelerators becomes a complex task. In fact, standard approaches require the construction of Finite State Machines whose complexity, in terms of number of states and transitions, increases exponentially with respect to the number of unbounded operations that may execute concurrently. We propose an adaptive architecture for such accelerators which overcome this limitation, while exploiting the available parallelism. The proposed design methodology is compared with FSM-based approaches by means of a motivational example.
Chair/Author Details:
Torsten Hoefler (Chair) - ETH Zurich
Vito Giovanni Castellana - Polytechnic University of Milan
Fabrizio Ferrandi - Polytechnic University of Milan
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Speeding-Up Memory Intensive Applications Through Adaptive Hardware Accelerators
SESSION: Research Poster Reception
EVENT TYPE:
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Torsten Hoefler
AUTHOR(S):Vito Giovanni Castellana, Fabrizio Ferrandi
ROOM:East Entrance
ABSTRACT:
Heterogenous architectures are becoming an increasingly relevant component for High Performance Computing: they combine the computational power of multi-core processors with the flexibility of reconfigurable co-processor boards. Such boards are often composed of a set of standard Field Programmable Gate Arrays (FPGAs), coupled with a distributed memory architecture. This allows the concurrent execution of memory accesses. Nevertheless, since the execution latency of these operations may be unknown at compile-time, the synthesis of such parallelizing accelerators becomes a complex task. In fact, standard approaches require the construction of Finite State Machines whose complexity, in terms of number of states and transitions, increases exponentially with respect to the number of unbounded operations that may execute concurrently. We propose an adaptive architecture for such accelerators which overcome this limitation, while exploiting the available parallelism. The proposed design methodology is compared with FSM-based approaches by means of a motivational example.
Chair/Author Details:
Torsten Hoefler (Chair) - ETH Zurich
Vito Giovanni Castellana - Polytechnic University of Milan
Fabrizio Ferrandi - Polytechnic University of Milan
Click here to download .ics calendar file