SCHEDULE: NOV 10-16, 2012
When viewing the Technical Program schedule, on the far righthand side is a column labeled "PLANNER." Use this planner to build your own schedule. Once you select an event and want to add it to your personal schedule, just click on the calendar icon of your choice (outlook calendar, ical calendar or google calendar) and that event will be stored there. As you select events in this manner, you will have your own schedule to guide you through the week.
Application Restructuring for Vectorization and Parallelization: A Case Study
SESSION: Research Poster Reception
EVENT TYPE: Posters and Electronic Posters
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Torsten Hoefler
AUTHOR(S):Karthik Raj Saanthalingam, David Hudak, John Eisenlohr, P. Sadayappan
ROOM:East Entrance
ABSTRACT:
Clock rates remain flat while transistor density increases, so microprocessor designers are providing more parallelism on a chip by increasing vector length and core count. For example, the Intel Westmere architecture has a vector length of four floats (128 bits) and six cores compared to eight floats (256 bits) and eight cores on the Intel Sandy Bridge. Applications must get good vector and shared-memory performance in order to leverage these hardware advances. Dissipative Particle Dynamics (DPD) is analogous to traditional molecular dynamics techniques applied to mesoscale simulations. We analyzed and restructured an existing DPD implementation to improve vector and OpenMP performance for the Intel Xeon and MIC architectures. We designed an efficient partitioned global address space (PGAS) implementation using the Global Arrays Toolkit using this experience. We present performance results on representative architectures.
Chair/Author Details:
Torsten Hoefler (Chair) - ETH Zurich
Karthik Raj Saanthalingam - Ohio Supercomputer Center
David Hudak - Ohio Supercomputer Center
John Eisenlohr - Ohio Supercomputer Center
P. Sadayappan - Ohio State University
Click here to download .ics calendar file
Click here to download .vcs calendar file
Click here to add event to your Google Calendar
Application Restructuring for Vectorization and Parallelization: A Case Study
SESSION: Research Poster Reception
EVENT TYPE:
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Torsten Hoefler
AUTHOR(S):Karthik Raj Saanthalingam, David Hudak, John Eisenlohr, P. Sadayappan
ROOM:East Entrance
ABSTRACT:
Clock rates remain flat while transistor density increases, so microprocessor designers are providing more parallelism on a chip by increasing vector length and core count. For example, the Intel Westmere architecture has a vector length of four floats (128 bits) and six cores compared to eight floats (256 bits) and eight cores on the Intel Sandy Bridge. Applications must get good vector and shared-memory performance in order to leverage these hardware advances. Dissipative Particle Dynamics (DPD) is analogous to traditional molecular dynamics techniques applied to mesoscale simulations. We analyzed and restructured an existing DPD implementation to improve vector and OpenMP performance for the Intel Xeon and MIC architectures. We designed an efficient partitioned global address space (PGAS) implementation using the Global Arrays Toolkit using this experience. We present performance results on representative architectures.
Chair/Author Details:
Torsten Hoefler (Chair) - ETH Zurich
Karthik Raj Saanthalingam - Ohio Supercomputer Center
David Hudak - Ohio Supercomputer Center
John Eisenlohr - Ohio Supercomputer Center
P. Sadayappan - Ohio State University
Click here to download .ics calendar file