SC12 Home > SC12 Schedule > SC12 Presentation - The practitioner's cookbook for good parallel performance on multi- and manycore systems

SCHEDULE: NOV 10-16, 2012

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The practitioner's cookbook for good parallel performance on multi- and manycore systems

SESSION: The practitioner's cookbook for good parallel performance on multi- and manycore systems

EVENT TYPE: Tutorials

TIME: 8:30AM - 5:00PM

Presenter(s):Georg Hager, Gerhard Wellein

ROOM:255-F

ABSTRACT:
The advent of multi- and manycore chips has led to a further opening of the gap between peak and application performance for many scientific codes. This trend is accelerating as we move from petascale to exascale. Paradoxically, bad node-level performance helps to "efficiently" scale to massive parallelism, but at the price of increased overall time to solution. If the user cares about time to solution on any scale, optimal performance on the node level is often the key factor. Also, the potential of node-level improvements is widely underestimated, thus it is vital to understand the performance-limiting factors on modern hardware. We convey the architectural features of current processor chips, multiprocessor nodes, and accelerators, as well as the dominant MPI and OpenMP programming models, as far as they are relevant for the practitioner. Peculiarities like shared vs. separate caches, bandwidth bottlenecks, and ccNUMA characteristics are pointed out, and the influence of system topology and affinity on the performance of typical parallel programming constructs is demonstrated. Performance engineering is introduced as a powerful tool that helps the user assess the impact of possible code optimizations by establishing models for the interaction of the software with the hardware on which it runs.

Chair/Presenter Details:

Georg Hager - Erlangen Regional Computing Center

Gerhard Wellein - Erlangen Regional Computing Center

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The practitioner's cookbook for good parallel performance on multi- and manycore systems

SESSION: The practitioner's cookbook for good parallel performance on multi- and manycore systems

EVENT TYPE:

TIME: 8:30AM - 5:00PM

Presenter(s):Georg Hager, Gerhard Wellein

ROOM:255-F

ABSTRACT:
The advent of multi- and manycore chips has led to a further opening of the gap between peak and application performance for many scientific codes. This trend is accelerating as we move from petascale to exascale. Paradoxically, bad node-level performance helps to "efficiently" scale to massive parallelism, but at the price of increased overall time to solution. If the user cares about time to solution on any scale, optimal performance on the node level is often the key factor. Also, the potential of node-level improvements is widely underestimated, thus it is vital to understand the performance-limiting factors on modern hardware. We convey the architectural features of current processor chips, multiprocessor nodes, and accelerators, as well as the dominant MPI and OpenMP programming models, as far as they are relevant for the practitioner. Peculiarities like shared vs. separate caches, bandwidth bottlenecks, and ccNUMA characteristics are pointed out, and the influence of system topology and affinity on the performance of typical parallel programming constructs is demonstrated. Performance engineering is introduced as a powerful tool that helps the user assess the impact of possible code optimizations by establishing models for the interaction of the software with the hardware on which it runs.

Chair/Presenter Details:

Georg Hager - Erlangen Regional Computing Center

Gerhard Wellein - Erlangen Regional Computing Center

Add to iCal  Click here to download .ics calendar file

Add to Outlook  Click here to download .vcs calendar file

Add to Google Calendarss  Click here to add event to your Google Calendar