SCHEDULE: NOV 10-16, 2012
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Hybrid Memory Cube (HMC): A New Paradigm for System Architecture Design
SESSION: Memory Systems
EVENT TYPE: Exhibitor Forums
TIME: 4:30PM - 5:00PM
DRAM technology has been utilized as main memory in microprocessor-based systems for decades. From the early days of frequency scaling, the gap has been growing between the DRAM performance improvement rate versus the processor data consumption rate. This presentation will show several advantages of using Micron’s Hybrid Memory Cube (HMC) technology. HMC is a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections. The HMC concept is completely re-architected, redistributing the normal DRAM functions while delivering: Scalable System Architectures: Flexible topologies (expandability) Abstraction - Future memory process scaling and challenges Performance: Higher effective DRAM bandwidth Lower DRAM system latency Increased DRAM random request rate Energy (Power-Efficient Architectures): Lower DRAM energy per useful unit of work done Reduced data movement Dependability (RAS): In-field repair capability Internal DRAM ECC
Todd Farrell - Micron Technology