SCHEDULE: NOV 10-16, 2012
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Tiling Stencil Computations to Maximize Parallelism
SESSION: Compiler-Based Analysis and Optimization
EVENT TYPE: Papers
TIME: 11:00AM - 11:30AM
SESSION CHAIR: Xipeng Shen
AUTHOR(S):Vinayaka Bandishti, Irshad Pananilath, Uday Bondhugula
Most stencil computations allow tile-wise concurrent start, i.e., there always exists a face of the iteration space and a set of tiling hyperplanes such that all tiles along that face can be started concurrently. This provides load balance and maximizes parallelism. However, existing automatic tiling frameworks often choose hyperplanes that lead to pipelined start-up and load imbalance. We address this issue with a new tiling technique that ensures concurrent start-up as well as perfect load-balance whenever possible. We first provide necessary and sufficient conditions on tiling hyperplanes to enable concurrent start for programs with affine data accesses. We then provide an approach to find such hyperplanes. Experimental evaluation on a 12-core Intel Westmere shows that our code is able to outperform a tuned domain-specific stencil code generator by 4 to 20 percent, and previous compiler techniques by a factor of 2x to 10.14x.
Xipeng Shen (Chair) - College of William & Mary
Vinayaka Bandishti - Indian Institute of Science
Irshad Pananilath - Indian Institute of Science
Uday Bondhugula - Indian Institute of Science