SCHEDULE: NOV 10-16, 2012
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Accelerating MapReduce on a Coupled CPU-GPU Architecture
SESSION: GPU Programming Models and Patterns
EVENT TYPE: Papers
TIME: 2:30PM - 3:00PM
SESSION CHAIR: Michael A. Heroux
AUTHOR(S):Linchuan Chen, Xin Huo, Gagan Agrawal
The work presented here is driven by two observations. First, heterogeneous architectures that integrate the CPU and the GPU on the same chip are emerging, and hold much promise for supporting power-efficient and scalable high performance computing. Second, MapReduce has emerged as a suitable framework for simplified parallel application development for many classes of applications, including data mining and machine learning applications that benefit from accelerators. This paper focuses on the challenge of scaling a MapReduce application using the CPU and GPU together in an integrated architecture. We use different methods for dividing the work, which are map-dividing scheme, which divides map tasks on both devices, and the pipelining scheme, which pipelines the map and the reduce stages on different devices. We develop dynamic work distribution schemes for both the approaches. To achieve high performance, we use a runtime tuning method to adjust task block sizes.
Michael A. Heroux (Chair) - Sandia National Laboratories
Linchuan Chen - Ohio State University
Xin Huo - Ohio State University
Gagan Agrawal - Ohio State University