SCHEDULE: NOV 10-16, 2012
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Three Steps to Model Power-Performance Efficiency for Emergent GPU-Based Parallel Systems
SESSION: Research Poster Reception
EVENT TYPE: Posters and Electronic Posters
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Torsten Hoefler
AUTHOR(S):Shuaiwen Song, Chun-Yi Su, Barry Rountree, Kirk Cameron
Massive parallelism combined with complex memory hierarchies form a barrier to efficient application and architecture design. These challenges are exacerbated with GPUs as parallelism increases an order of magnitude and power consumption can easily double. Models have been proposed to isolate power and performance bottlenecks and identify their root causes. However, no current models combine usability, accuracy, and support for emergent GPU architectures (e.g. NVIDIA Fermi). We combine hardware performance counter data with machine learning and advanced analytics to create a power-performance efficiency model for modern GPU-based systems. Our performance counter based approach is general and does not require detailed understanding of the underlying architecture. The resulting model is accurate for predicting power (within 2.1%) and performance (within 6.7%) for application kernels on modern GPUs. Our model can identify power-performance bottlenecks and their root causes for various complex computation and memory access patterns (e.g. global, shared, texture).
Torsten Hoefler (Chair) - ETH Zurich
Shuaiwen Song - Virginia Tech
Chun-Yi Su - Virginia Tech
Barry Rountree - Lawrence Livermore National Laboratory
Kirk Cameron - Virginia Tech