SCHEDULE: NOV 10-16, 2012
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How to Analyze the Performance of Parallel Codes 101
SESSION: How to Analyze the Performance of Parallel Codes 101
EVENT TYPE: Tutorials
TIME: 8:30AM - 12:00PM
Presenter(s):Martin Schulz, Jim Galarowicz, Don Maghrak, David Montoya, Mahesh Rajan, Matthew LeGendre
Performance analysis is an essential step in the development of HPC codes. It will even gain in importance with the rising complexity of machines and applications that we are seeing today. Many tools exist to help with this analysis, but the user is too often left alone with interpreting the results. In this tutorial we will provide a practical road map for the performance analysis of HPC codes and will provide users step by step advice on how to detect and optimize common performance problems in HPC codes. We will cover both on-node performance and communication optimization and will also touch on accelerator based architectures. Throughout this tutorial will show live demos using Open|SpeedShop, a comprehensive and easy to use performance analysis tool set, to demonstrate the individual analysis steps. All techniques will, however, apply broadly to any tool and we will point out alternative tools where useful.
Martin Schulz - Lawrence Livermore National Laboratory
Jim Galarowicz - Krell Institute
Don Maghrak - Krell Institute
David Montoya - Los Alamos National Laboratory
Mahesh Rajan - Sandia National Laboratories
Matthew LeGendre - Lawrence Livermore National Laboratory