SC12 Home > SC12 Schedule > SC12 Presentation - Exploring Design Space of a 3D Stacked Vector Cache

SCHEDULE: NOV 10-16, 2012

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ENTIRE WEEK SATURDAY SUNDAY MONDAY TUESDAY WEDNESDAY THURSDAY FRIDAY

Exploring Design Space of a 3D Stacked Vector Cache

SESSION: Research Poster Reception

EVENT TYPE: Posters and Electronic Posters

TIME: 5:15PM - 7:00PM

SESSION CHAIR: Torsten Hoefler

AUTHOR(S):Ryusuke EGAWA, Yusuke Endo, Jubee Tada, Hiroyuki Takizawa, Hiroaki Kobayashi

ROOM:East Entrance

ABSTRACT:
This paper explores and presents a design method of a 3D integrated memory system using conventional EDA tools. In addition, to clarify the potential of TSVs, delay and power consumption of TSVs are quantitatively evaluated, and are compared with those of conventional 2D wires under various CMOS process technologies. The main contributions of this paper are; 1) clarifying the potential of TSVs based on the SPICE compatible simulations, 2) exploring the design methodology of a 3D integrated memory system using conventional EDA tools, and 3) quantitatively comparing 3D integrated cache memories with 2D ones.

Chair/Author Details:

Torsten Hoefler (Chair) - ETH Zurich

Ryusuke EGAWA - Tohoku University

Yusuke Endo - Tohoku University

Jubee Tada - Yamagata University

Hiroyuki Takizawa - Tohoku University

Hiroaki Kobayashi - Tohoku University

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